FIG. 1 is a block diagram showing a conventional semiconductor integrated circuit FIG. 1, memory cells (MC) 3 are selected by a word line 2, and one of them is accessed by complementary bit lines L Bit lines 1 are connected to column switches 5 which are turned on/off by a column switch control (CC) signal 4. Each memory cell 3 is connected to bit lines 1 and a word line 2 as shown in the circuit diagram of FIG. 2. One of memory cells 3 selected by the word line 2 is accessed by the bit lines 1.
The circuit arrangement shown in PIG. 1 is generally called a word line control system. With this system, when one word line 2 is selected, all memory cells 3 connected to this word line 2 are activated Therefore, there arises the problem of a large load and hence large consumption current.
A circuit eliminating the above problem is known which has the structure as shown in FIG. 3. In this circuit, memory cells are divided into blocks of several memory cell array sections 9. An access signal from a main word line 6 is selected by using a section select line 8, and connected to a section word line 7 provided for each array section 9. As shown in the block diagram of FIG. 4, in each array section 9, a NOR gate executes a logical operation between signals on the main word line 6 and the section select line 8, to select a particular section word line 7. Memory cells 3 selected by the section word line 7 are being disposed in a similar manner as shown in FIG. 1. Each memory cell 3 is accessed by controlling column switches connected to the bit lines 1 upon reception of a column switch control signal 4.
With the above-described arrangement, the section word line 7 in each memory cell array section 9 is selected in accordance with the logical condition between the main word line 6 and section select line 8. Memory cells 3 connected only to the selected section word line 7 are activated, allowing reduced load and consumption current.
Conventional semiconductor integrated circuits have been structured in the manner just described above. Therefore, in order to select a particular one of section word lines 7 of each array section 9, it is necessary to provide logical circuits for obtaining logical conditions between the main word line 6 and section selection lines 8. These logical circuits are connected to the section select lines 8, posing another problem of a large load on the section selection line 8. The section select line 8 is usually connected to the gates of transistors each of which outputs a select signal to the corresponding section word line 7. However, the gate capacitance of such a transistor is substantially large, and the select speed is lowered essentially. Particularly in the case where the section select line 8 is driven by a CMOS inverter, the load becomes excessively heavy, resulting in a low access speed.